The design of personal electronic devices, such as cell phones and hand held computers, require significant power conditioning and regulation. These processes are facilitated through the application of power semiconductor devices which can handle relatively high current. Historically these power semiconductor devices have been restricted to the amount of current that they can conduct, because the heat associated with the current transfer can damage the device causing reliability issues. The industry standard package for power semiconductor devices is the “SO-8”, an eight pin, surface mounted, plastic enclosed device. The demand for higher frequencies and stronger wireless connections has stressed this technology to the breaking point.
Heat management improvements in power discrete semiconductor packages, in particular for DC-DC or DC-AC converters, have seen slow progress. These converters often employ multiple parallel SO-8 devices, such as synchronous rectifiers, due to printed circuit board (PCB) real estate constraints. The layout of the PCB becomes congested due to the parallel arrangement of the original legacy power packages. Traditionally in SOIC leaded form, an SO-8 package is thermally inferior in handling high current and high power devices. Typically, the junction-to-solder point thermal resistance of an SO-8 device is in the range of 20 k/W to 30 k/W, depending on the chip size and current rating. The junction-to-mounting base thermal resistance of a TO 251/252 or PowerPAK device is usually in the range of 2 k/W to 3 k/W. This means the inferior thermal capability of the SO-8 package has necessitated the need to arrange multiple devices in parallel to spread the power dissipation and prevent any one device from running too hot. Unfortunately, the parallel arrangement of many devices on the PCB, may also lead to excessive source-to-drain current discharges in the connecting MOSFET drivers, as well as having negative impact on the converter's overall efficiency.
Vertically stacking SO-8 packages together does not improve heat dissipation capability. The current design of SO-8 packages in the market place, either leaded or leadless version, has no electrical connecting terminals on top of the package surface that links the device common Source (S), Gate (G) or Drain (D) when being stacked package-on-package (PoP). Having mold compound abraded together for PoP purpose leads to higher heat storage capacity, opposing the trend for integrating more heat dissipation features to achieve faster device cooling effect. The technology trends are clearly adding stress to the power semiconductor market. Packaging redesign in terms of form factor change and thermal management is needed to deliver the latest power devices needed by today's market.
Thus, a need still remains for a system of stackable power semiconductor package. In view of the demand to shrink device form factors on PCB's and increase the power dissipation capabilities, it is increasingly critical that answers be found to these problems. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.